<prev

NL09S1XX
Analog computational circuits for finite set theory
Development Boards

next>

NL09S1XX Datasheet (7/1/09)
PDF [3 MB]
NL09S1XX Specifications (7/1/09)
Word [488 kB]
NL09S1XX Theory (7/1/09)
Word [488 kB]

Design principles and operation

The NL09S1XX development boards implement analogues of expressions in Set Theory. Expressions in set theory are generally relatively simple, involving a relatively small number of sets constrained by standard operations such as intersection, union, and set difference. Examples of such expressions are shown here:

If we restrict ourselves to core operations, we can assemble almost any compound expression using a relatively small number of canonical operations. We can then define simple circuit fragments that are the analogues of each canonical set theory operation. The following figure shows the circuit fragments for the 8 standard set theory operations: intersection, union, difference, symmetric difference, equality, subset, proper subset, and inverse.

In the left figure above, we show the circuit analogues in current-mode; there is an entirely equivalent set for voltage-mode. In the right figure above, these 8 circuit fragments are rewritten in the form of dual-input/output modules, and the 4 first-order logic functions (complement, equals, and, or) are included. The set theory operations intersection, union, difference, symmetric difference, and inverse give output that is a member of a new set; all other functions shown above give Boolean logical outputs.

Now given any set of expressions, it is a simple matter to connect the circuit fragments in the same topology as the expressions. For instance, the pair of expressions


gives the following circuit, obtained by merely connecting the circuit fragments in the same topology as the expressions (and adding the Boolean AND gate):


The example above is drawn using the current-mode circuit fragments. Using the dual-input/output modules, such circuits can be organized in a systematic and simpler way, illustrated here for two examples:

Circuits assembled from the canonical fragments are analogues of the complete set theory expressions; we will call them circuit expressions. The circuits are guaranteed to be faithful representations of the set theory expressions, by construction.

The NL09S1XX product series provides implementations of circuit expressions, using the above modules and design procedure. Signals are provided to pins that enable jumper connections within the modules and to other modules. While the circuits process the sets as analog signals, they really should be considered mixed-signal, because some of the set theory expressions, and all the logical expressions, give Boolean outputs. Overlay boards are available that provide default connections for some common connectivities.

NL09S130C - 30-module development board (current mode)
NL09S130V - 30-module development board (voltage mode)

The NL09S130 development board comprises 30 functional modules, each with 1 or 2 inputs and 1 output. The modules can be configured to implement any of the operations in set theory or the logical operations. The NL09S130C operates in current mode, while the NL09S130V operates in voltage mode. The board is fabricated with a backplane of pins, allowing the manual wiring of a desired topology using jumpers. The board is programmed via the edge connector. A connector at the top edge provides signals that can be used for monitoring the state of the computation.

Applications of the NL09S100 include algorithm development for hybrid data processing, domain-limited set theory proofs, fuzzy-set computations, analog control, and research on analog precision.

These products are implemented according to the principle of TOPOLOGICTM, in which the circuit has structure and function that are analogues of the physical system. The modules are generally constructed to be data transfer units, enabling direct coupling of modules in exact correspondence with expressions in set theory. NanoLogic is the inventor of this technology, which is protected by U. S. patents (pending).